Hardware notes for sheet 2 - SDRAM
This sheet shows the two SDRAM DIMM sockets, together with their required buffering and address multiplexor. It is a 3.3V only page and has one set of bypass capacitors. The signals on this page are mostly running at 66MHz, so high speed design rules must be applied to the layout.
- The design uses 100MHz (10ns) SDRAMs clocked at 66MHz in CAS latency 2 mode. The 100MHz speed grade is needed to allow the 2 cycle latency, slower parts would force use of CAS latency 3, adding an extra cycle to the start of every access.
- Each168 pin DIMM slot should work with a modules between 4Mbyte and 32Mbyte. To enable this the address lines are connected in a careful manner as described in the PAL source code.
- The data bus for the StrongARM is only 32 bits wide, whereas the JEDEC DIMM standard is for 64 bit wide modules. According to the standard the ~cs0 input enables devices that drive data lines [0..15,32..47] as does ~cs1 for larger modules. The ~cs2 line enables devices that drive data lines [16..31,48..63] as does ~cs3 on larger modules. For 32 bit wide operation we common these blocks of data lines and ensure that only one ~cs is ever asserted.
- The modules have a small serial EEPROM containing information about the module configuration, speed, etc.This is accessed using an I2C bus controlled by software. The I2C bus address for the EEPROMs is 1010000 for one socket and 1010001 for the other, the low three bits of the address are set by the SA0-2 input lines.
- The design uses JEDEC standard 168-pin unbuffered 3.3V 100MHz SDRAM DIMMs, and this speed grade has been used for all testing. The provisional specs for the Samsung DIMMs indicate that their 83MHz (12ns) parts should also work This has not been tested, and the specs may have changed.
- For rev 3 and later boards, the following module configurations are supported:
- 8MB 1 bank, 1Mx64bit (this is the base we have been using)
- 16MB 1 bank, 2Mx64bit (we have tested these)
- 16MB 2 bank, 1Mx64bit (we have tested these)
- 32MB 2 bank, 2Mx64bit (these are standard "software development" configuration)
- For rev 4 and later boards (or rev 3 if you have the right control PAL :-), the following module configurations are also supported:
- 32MB 1 bank, 4Mx64bit (We have not seen *any* of these)
- 64MB 2 bank, 4Mx64bit (We have tried a couple of these)
- For rev 1 boards the options are fairly limited for upgrading. It's possible to get as much as 64MB if you can find the right DIMMs. The problem is that rev 1 boards only support single bank DIMMs. Rev 3 and later support both single and dual bank DIMMs, offering much more flexibility.
Here are your choices for rev 1:
- 8MB 1 bank, 1Mx64bit
- 16MB 1 bank, 2Mx64bit
- 32MB 1 bank, 4Mx64bit (theoretical, we have never seen one)
- Another thing to watch out for if you deal with anyone other than first-tier memory vendors is DIMMs that don't conform to the JEDEC standard. The DIMMs are 64-bits wide, but each select line controls 32-bits. We bought some DIMMs from "Memories-R-Us" [not the real name] that didn't have the select lines controlling the correct 32-bits. These DIMMs will work fine in systems that access 64-bits at a time (which are in fact most systems that the DIMMs will be used in), but they don't work in DNARD. Caveat emptor.
- Two 18 bit wide data buffers are used rather than the expected 16 bit wide ones. This is because the 16 bit devices are byte-oriented and each would place four loads on the clock, rather than the two loads the chosen buffers use.
- The byte enable lines are buffered through a tri-state buffer. This is both used to provide the fan-out drive for modules with many chips and to allow easy deasertion of all DQMB lines during reset and machine initialization. The bootmd (boot mode) signal is used to disable the dimms data path while the hardware state machines are initialized.
Address Latch and mux
- As with all DRAMs a multiplexed address is required. Two simple multiplexer devices are used to do the higher address bits, the PAL generates the three low order bits. For the range of modules supported A11-12 are only used at ras time so need not be muxed.
- To allow both the CPU burst sequence and a 486 DMA burst sequence the PAL generates the address for all CAS cycles, so the cas address bits must be valid at the start of all cas cycles.
- The address latch is closed to hold the column address because the cpu may change the address early prior to the last word of an access.
- The a10ap signal is used to provide SDRAM address A10 during RAS time, and the auto-precharge command during CAS time. Since we never use auto-precharge, we always send a logic low during CAS.
Updated: 2nd September 1997
Copyright (c) 1997 by Digital Equipment Corporation
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